The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design Data_Converter_In_FIFO.vhd. The design Data_Converter_In_FIFO.vhd has a depth of 256 words of 17 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.
The above waveform shows the behavior of the design under normal read and write conditions with aclr .
The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back.